1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a technique for forming metal interconnect lines on integrated circuits.
2. Description of the Prior Art
As integrated circuit devices become more complex, greater numbers of interconnect levels are required to connect the various portions of the device. Complex devices are being designed which have two or more levels of polycrystalline silicon interconnect, followed by one or more levels of metal interconnect. When multiple layers of interconnect are used in this manner, difficulties are encountered in forming upper interconnect levels because of uneven topographical features caused by lower interconnect levels. Thus, topography of interconnect layers affects the ease of manufacturing of the integrated circuit device.
In order to make forming upper interconnect levels easier, planarization of lower interconnect levels is routinely performed. Typically, a layer of material such as a reflow glass or spin on glass can be used as part of an interlevel dielectric layer. These materials, when applied properly, have an upper surface which is smoother and more nearly planar than the topography of the underlying surface. This allows the roughness caused by underlying interconnect layers to be smoothed out somewhat prior to the formation of the next layer of interconnect. This next layer of interconnect is then formed on top of the planarized interlevel dielectric layer. Even with this technique, step coverage problems exist since formation of the interconnect layer on the planarized dielectric layer generates uneven topographical features for the next dielectric layer, requiring further planarization. In addition, the planarization improves the flatness of the surface, but does not completely eliminate hills and valleys caused by underlying topographical features.
Various other techniques have been used in the past in an attempt to planarize interconnect as much as possible. One such technique is shown, for example, in U.S. Pat. No. 4,508,815, issued to Ackmann, et al, entitled RECESSED METALIZATION. In this patent, a lift off technique is used to form signal lines which are already somewhat recessed within an oxide layer. This is done is an attempt to improve planarity of the overall device. However, such techniques are difficult to use, and there can be some reliability problems with the resulting product.
It would be desirable for a technique for forming metal interconnect lines to provide such interconnect which is very nearly planar on its upper surface. It is desirable for such a technique to be compatible with present day manufacturing processes, and be relatively simple to use. It is important that such a process provide metal signal lines which are free of voids and other defects.